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Design Of Advanced Encryption Standard (AES) Algorithm Using Verilog

1.ATMAKURI KHANDESWARA RAO

PG Studies, Department of Electronics communication and Engineering, JNTUK

University College. Paladugu Parvathi Devi College of Engineering & Technology Vijayawada, India

Email:khandeswararao99@gmail.com

2.Mr.PARASHURAMA.N Associative Professor,

Department of electronics communication and Engineering,

JNTUK University College. Paladugu

Parvathi Devi College of Engineering & Technology Vijayawada, India   Email:parashu.ppdv@gmail.com

3. Miss. PRASHANTHI M Assistant professor,

JNTUK University College. Vikas Group of Institutions VIJAYAWADA, India

Email:shanti.maddala09@gmail.com

Abstract—Moved Encryption Standard (AES), a Federal Information Processing Standard (FIPS), is an embraced cryptographic count that is used to make sure about electronic data. Right now data, need for protection of information is more articulated than any time in recent memory. Secure correspondence is important to protect sensitive data in military and government organizations just as private people. Current encryption gauges are utilized to encode and ensure information during transmission as well as capacity too.

This paper offers a technique for combining encrypted and decrypted AES data. This approach may reduce the complexity of the design, particularly in terms of hardware resources required to implement the AES Sub Bytes and Mix columns modules, among other things. AES encryption and decryption are supported by the majority of modules. Moreover, in both encryption and decryption processes, the architecture can still provide a high data rate

KEYWORDS: ENCRYPTION, CRYPOTOGRAPHY, MODELSIM, AES, FPGA,VERILOG