Design and Synthesis of 64-Bit Vedic Multiplier using Kogge-Stone Prefix Adder

Ms. K. Vasantha Laxmi1, M Umamaheswari2, N Riyaz Shaik 3, C Sai Prathyusha Reddy4,
G Mohith Kumar5
1M. Tech, ECE Department, Annamacharya Institute of Technology and Sciences, Tirupati,
vasanthalaxmik1998@gmail.com
2B. Tech, ECE Department, Annamacharya Institute of Technology and Sciences, Tirupati,
umamuthyala71@gmail.com
3B. Tech, ECE Department, Annamacharya Institute of Technology and Sciences, Tirupati,
riyazshaik53002@gmail.com
4B. Tech, ECE Department, Annamacharya Institute of Technology and Sciences, Tirupati,
chithamreddyprathyusha@gmail.com
5B. Tech, ECE Department, Annamacharya Institute of Technology and Sciences, Tirupati,
gettipatimohithkumar@gmail.com

Abstract - A high-speed 64-bit Vedic multiplier based ontheUrdhvaTiryakbhyamalgorithmispresentedinhiswork.Themultiplierisimplemented using a hierarchical architecture, where 2, 4 , 8, 16, and 32-bit multiplier blocks are recursively combined to construct the 64-design,enabling modularity and efficient reuse of hardware. Carryartificial intelligence, and high-speed computing systems. As modern applications demand faster data processing, designing high-performance multipliers for large bit widths, such as 64-bit, has become increasingly important inVLSI design