Design of an FPGA-Based SPI Master Controller Supporting Multiple Slave Devices

D. Jithendra Reddy
Department of ECE, Annamacharya Institute of Technology and Sciences
(Autonomous), Tirupati,AP,Indiajithendrareddy.d@gmail.com
T. Manasa
Department of ECE,Annamacharya Institute ofTechnology and Sciences
(Autonomous), Tirupati,AP,Indiamanasat355@gmail.com
D. Mounika
Department of ECE,Annamacharya Institute ofTechnology and Sciences
(Autonomous), Tirupati,AP,Iniaderangulamouni2@gmail.com

M. Manasa
Department of ECE,Annamacharya Institute ofTechnology and Sciences
(Autonomous), Tirupati,AP,Indiamedapurammanasa9@gmail.com

V. Lohith Vardhan
Department of ECE,Annamacharya Institute ofTechnology and Sciences

(Autonomous), Tirupati,AP,Indiavardhanlohid

Abstract— Serial Peripheral Interface (SPI) is a common synchronous data transmission protocol in high-speed data transfer among digital devices in embedded systems. The paper gives the design and implementation of a Single Master Multiple Slave (SMMS) SPI environmentusing FPGA to enhance scalability and flexibility of communication than the traditional Single Master Single Slave (SMSS) SPI frameworks. The given design allows a single master controller to interact with other slave devices through common communication lines like MOSI, MISO, and SCLK, whereas the peculiar chip select signals are utilized to turn-on of certain slave modules. The SPI master and slave modules are developed in Verilog Hardware Description Language (HDL) and done in a Xilinx Kintex-7 FPGA (xc7k160tfbg676-2) with AMD Vivado 2023.1. Simulation validation shows that there was a functional communication between the master and four slave devices with proper data transmission and reception.