FPGA Based 64-Bit Floating Point Multiplier using Carry Look Ahead Adder

Dr.K.Janshi Lakshmi Associate
Professor Dept of ECE Annamacharya Institute of Technology and Sciences
Tirupati, India jansikaramala@gmail.com
Doddarapu Nithin B tech Student
Dept of ECE Annamacharya Institute of Technology and Sciences
Tirupati, India d.nithin034@gmail.com
Varadarajulu Navya B tech Student
Dept of ECE Annamacharya Institute of Technology and Sciences
Tirupati, India varadharajunavya@gmail.com
Kummaragunta Lasya Priya B tech
Student Dept of ECE Annamacharya Institute of Technology
and Sciences Tirupati, India lasyapriyak2005@gmail.com
Pokuru Mohanendra B tech Student Dept of ECE
Annamacharya Institute of Technology and Sciences
Tirupati, India mohanendra.p@gmail.com

Abstract: Floating-point arithmetic plays a crucial role in digital signal processing (DSP) and high-performance computing applications, where accuracy and speed are critical. Among floating-point operations, multiplication is one of the most complex and time-consuming processes. This paper presents the design and implementation of a 64-bit IEEE-754 double-precision floating point multiplier employing a Carry Look-Ahead Adder (CLA) to improve computational speed. The proposed architecture performs sign calculation, exponent addition with bias adjustment, mantissa multiplication, normalization, and rounding in accordance with the IEEE-754 standard. By using a CLA in the addition stages, carry propagation delay is significantly reduced compared to conventional ripple carry adders,  esulting in enhanced performance. The design is modeled and verified using verilog and synthesized on an FPGA platform. Experimental results demonstrate that the proposed 64-bit floating-point multiplier achieves higher speed and better precision, making it suitable for high speed applications such as filtering, signal analysis, and scientific computations. Keywords: Floating-point multiplier, IEEE-754 standard, 64- bit double precision, Carry Look-Ahead Adder, FPGA implementation.