Single Cycle Risc-V Processor Using Verilog

N.M.Hatte1, V.VKesarkar2, S.D.Chirke3, S.S.Kanse4

1UG Scholar, Dept. of ECE, KIT’s College of Engineering, Kolhapur, Maharashtra, India

2UG Scholar, Dept. of ECE, KIT’s College of Engineering, Kolhapur, Maharashtra, India

3UG Scholar, Dept. of ECE, KIT’s College of Engineering, Kolhapur, Maharashtra, India

4UG Scholar, Dept. of ECE, KIT’s College of Engineering, Kolhapur, Maharashtra, India

Abstract - This paper describes the design and implementation of RISC-V processor with single cycle using Verilog hardware description language. This processor is based on the RISC-V instruction set architecture (ISA). It is easy to understand, flexible, open for use and development. All instructions are executed in a single clock cycle. Main functional blocks such as Arithmetic Logic Unit (ALU), register file, control unit, instruction memory and data memory are included in the design. The processor can execute basic RISC-V instructions including arithmetic operations, logical operations, memory access and branch operations. The implementation describes the basic operation of a RISC-V processor and helps for understanding the modern processor architecture. The proposed system can be further extended for pipelining and advanced processor features in future work.

Key Words: RISC-V Processor, Single Cycle Processor, Verilog HDL, Instruction Set Architecture (ISA), ALU.