Design & Verification of a Weighted Round-Robin Arbiter Using System Verilog

Nagamani ¹, Dr.Basavalinga Swamy ² , Dr.Sharanbasappa Shetkar ³  , Dr.Vinita Patil ⁴ ,

Prof .Sadhana C⁵

¹Nagamani Dept. of VLSI Design and Embedded system, M.Tech student, LAEC, Bidar

²Dr.Basavalinga Swamy, Associate Professor, Department of ECE, LAEC Bidar

⁴Dr.Sharanbasappa Shetkar, Professor, Department of ECE, LAEC Bidar

⁴Dr.Vinita Patil, Professor, Department of ECE, LAEC Bidar

⁵Prof .Sadhana C, Assistant Professor, Department of ECE, LAEC Bidar

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Abstract – The increasing complexity of modern digital systems and System-on-Chip (SoC) architectures has intensified the demand for efficient arbitration mechanisms to manage simultaneous access to shared communication resources. Conventional Round-Robin (RR) arbiters provide fair access among multiple requesters; however, they are unable to satisfy applications that require unequal bandwidth allocation or differentiated Quality of Service (QoS). To address this limitation, this paper presents the design and verification of a Weighted Round-Robin (WRR) Arbiter using SystemVerilog. The proposed architecture assigns configurable weights to individual requesters, enabling bandwidth distribution according to application requirements while preserving fairness and preventing starvation. The arbiter is implemented using synthesizable SystemVerilog RTL and verified through a comprehensive self-checking testbench. Multiple test scenarios, including simultaneous requests, varying weight configurations, continuous traffic, and idle conditions, are used to evaluate the functional correctness of the design. Simulation results demonstrate accurate grant generation, proper weight management, efficient pointer rotation, and reliable arbitration behavior under different operating conditions. The modular design offers low hardware complexity, scalability, and compatibility with FPGA and ASIC implementation, making it suitable for high-performance embedded systems, bus interconnects, memory controllers, and Network-on-Chip (NoC) applications.

KeyWords: Weighted Round-Robin Arbiter, SystemVerilog, Resource Arbitration, Round-Robin Scheduling, RTL Design, Digital System Design, FPGA, ASIC, Verification, Self-Checking Testbench, Multi-Master Bus, System-on-Chip (SoC)