A Novel Design of Power-Efficient and Accurate Approximate Multiplier using Approximate Compressors and Approximate Adders
A Novel Design of Power-Efficient and Accurate Approximate Multiplier using Approximate Compressors and Approximate Adders
Mrs. C. Munikantha1, C. Prathyusha2, B. Sudarshan3, N. Sasidhar Raju4, M. Purushotham5
1 Assistant Professor, Department of Electronics & Communication Engineering , Annamacharya Institute Of Technology &Sciences, Tirupati, Andhra Pradesh, India, chinthaguntamuni9@gmail.com
2 U.G Scholar, Department of Electronics & Communication Engineering , Annamacharya Institute Of Technology & Sciences, Tirupati, Andhra Pradesh, India, prathyushac75@gmail.com
3 U.G Scholar, Department of Electronics & Communication Engineering , Annamacharya Institute Of Technology & Sciences, Tirupati, Andhra Pradesh, India, birrusudarshan777@gmail.com
4 U.G Scholar, Department of Electronics & Communication Engineering , Annamacharya Institute Of Technology & Sciences, Tirupati, Andhra Pradesh, India, sasidharraju867@gmail.com
5 U.G Scholar, Department of Electronics & Communication Engineering , Annamacharya Institute Of Technology & Sciences, Tirupati, Andhra Pradesh, India,purushothampurna123@gmail.com
Abstract – This paper proposes a novel design of a power- efficient and accurate approximate multiplier that utilizes the concepts of approximate compressors and adders. In many applications, such as image processing, neural networks, and wireless communications, the requirement of precision may not be high. Therefore, the use of approximate computing techniques may be used to improve the performance and reduce the power consumption. In this paper, the design of the multiplier is simplified with the use of approximate logic blocks, which include the use of approximate half adders, full adders, and compressors. In addition, the design includes an error compensation mechanism that ensures the design is accurate. In this paper, the design is coded using Verilog HDL and then simulated and synthesized using the Xilinx Vivado tool. The simulation results reveal that the designs proposed in this paper significantly reduce the power consumption while ensuring the accuracy of the designs. In this paper, the proposed design is compared with the existing designs, where the power consumption is reduced by 59.16% and 65.93%, with average accuracies of 93.14% and 91.98%,respectively.Keywords: Reduced power, Increased speed, Decrease area, Accuracy is increased.