AN EFFICIENT VLSI DESIGN OF FIR FILTER IMPLEMENTATION BASED ON VARIOUS MULTIPLIERS: A REVIEW

Notification

Announcement!

ISJEM Invites papers for various areas like engineering, Management, Science & other multi discplinary subjects. Please submit your paper for review.

ISJEM assigns a digital object identifier (DOI) to each published paper, making it easier for the paper to be cited in various major databases like Google Scholar, ResearchGate, Academia.edu, etc…

ISJEM takes 24–48 hours to publish a research paper. Within 24 hours, the submitted paper will be reviewed and notified of its status, and it will be published once the processing fee is successfully received.

AN EFFICIENT VLSI DESIGN OF FIR FILTER IMPLEMENTATION BASED ON VARIOUS MULTIPLIERS: A REVIEW

Version
Download 9
File Size 447.63 KB
File Count 1
Create Date 28 May 2023
Last Updated 28 May 2023

AN EFFICIENT VLSI DESIGN OF FIR FILTER IMPLEMENTATION BASED ON VARIOUS MULTIPLIERS: A REVIEW

Prince Yadav, Sandeep Kumar Kushwaha, Hritik Gupta, Mr. Yatheesh KC

Department of ECE

JSS Academy of Technical Education

NOIDA, INDIA

Abstract – Area optimization and power consumption reduction are the two most crucial considerations in the designing and implementation of any DSP processors. The FIR Filter serves as the essential building block for the designing and developing the DSP processors. The three fundamental modules that make up the FIR Filter are: Multiplier block, Adder block and Flip flops.The multiplier, the slowest block of all, has a significant impact on the FIR Filter's performance. Array multiplier, booth multiplier, and a combination technique have all been used to create the FIR Filter that has been proposed in this paper (Karatsuba and Urdhva Tiryagbhyam) and discovered that the combined method is more efficient than the compared algorithms because it has less delay, which speeds up binary multiplication.

Download