International Scientific Journal of Engineering and Management

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AN EFFICIENT VLSI DESIGN OF FIR FILTER IMPLEMENTATION BASED ON VARIOUS MULTIPLIERS: A REVIEW

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AN EFFICIENT VLSI DESIGN OF FIR FILTER IMPLEMENTATION BASED ON VARIOUS MULTIPLIERS: A REVIEW

Prince Yadav, Sandeep Kumar Kushwaha, Hritik Gupta, Mr. Yatheesh KC

Department of ECE

JSS Academy of Technical Education

NOIDA, INDIA

 

Abstract – Area optimization and power consumption reduction are the two most crucial considerations in the designing and implementation of any DSP processors. The FIR Filter serves as the essential building block for the designing and developing the DSP processors. The three fundamental modules that make up the FIR Filter are: Multiplier block, Adder block and Flip flops.The multiplier, the slowest block of all, has a significant impact on the FIR Filter's performance. Array multiplier, booth multiplier, and a combination technique have all been used to create the FIR Filter that has been proposed in this paper (Karatsuba and Urdhva Tiryagbhyam) and discovered that the combined method is more efficient than the compared algorithms because it has less delay, which speeds up binary multiplication.


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