Design and FPGA Implementation of 4×4 Vedic Multiplier using Different Architectures

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Design and FPGA Implementation of 4×4 Vedic Multiplier using Different Architectures

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Create Date 27 April 2024
Last Updated 27 April 2024

Design and FPGA Implementation of 4x4 Vedic Multiplier

using Different Architectures

shyam sundhar¹, K.akhil2, N.suresh³, T.sravan kumar ⁴, Mr. S. Rambabu⁵

¹²³⁴IV B. Tech, ECE Department, Santhiram Engineering College.

⁵Assistant Professor, ECE Department, Santhiram Engineering College.

Abstract - The need of high speed multiplier is increasing as the need of high speed processors are increasing. A Multiplier is one of the key hardware blocks in most of the fast processing systems which is not only a high delay block but also a major source of power dissipation. A conventional processor requires substantially more hardware resources and processing time in the multiplication operation, rather than addition and subtraction. This Project describes about the design of 4-bit, 8-bit and 32-bit Vedic multiplier using ancient Vedic mathematics which helps in delay and power reduction. Simulation is done in Xilinx VIVADO software using VHDL and display on LCD. The results for Vedic multiplier using various architecture and their delay comparison are done.

Key Words: FPGA (Artix-7), adders, 4x4 Array Multiplier, Vedic Mathematics

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