Design and Implementation of 5-Stage pipelined RISC-V Embedded Processor

Mr.Nagaraju Rangappagari
Assistant Professor Dept of ECEAnnamacharya Institute of Technology
and SciencesTirupati, Indiar.nagarajuece@gmail.com
Gunduboyana Sravani B Tech
Student Dept of ECEAnnamacharya Institute of Technology
and Sciences Tirupati,Indiagunduboyanasravani@gmail.com
Kunati Sahithi B Tech Student Dept
of ECEAnnamacharya Institute ofTechnology and Sciences
Tirupati,Indiasahithis013@gmail.com
V.SarathChandra B Tech Student
Dept of ECEAnnamacharya Institute ofTechnology and Sciences
Tirupati,Indiasarathsai@gmail.com

Mavilla Triveni B Tech Student Dept ofECE
Annamacharya Institute of Technologyand Sciences Tirupati,Indiatrivenimavilla@gmail.com

Abstract—This paper presents the design and implementation of a 32-bit 5-stage pipelined RISC-V embedded processor based on the RV32I instruction set architecture. The processor follows the classical pipeline stages: Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Write Back (WB) to improve instruction throughput and overall computational fficiency. To enhance pipeline performance, a hazard detection unit and forwarding paths are incorporated to resolve data hazards and minimize pipeline stalls. Control hazards are handled through branch target address computation and pipeline flushing mechanisms.