Design and Implementation of a Single-Cycle RV32I Processor using Verilog HDL

A. S. Lavanya 1, S. Bindusagar2, P. Haritha3, P. Ganesh4, K. Gnaneswar5
1Assistant Professor, Department of ECE, Annamacharya Institute of Technology and Sciences, Tirupati,
Andhra Pradesh, India, lavanya04.aits@gmail.com
2Student Department of ECE, Annamacharya Institute of Technology and Sciences, Tirupati, Andhra Pradesh,
India, sbindusagar2003@gmail.com
3Student Department of ECE, Annamacharya Institute of Technology and Sciences, Tirupati, Andhra Pradesh,
India, harithaponna15@gmail.com
4Student Department of ECE, Annamacharya Institute of Technology and Sciences, Tirupati, Andhra Pradesh,
India, dreamboyganesh29@gmail.com
5Student Department of ECE, Annamacharya Institute of Technology and Sciences, Tirupati, Andhra Pradesh,
India, kambakamgnaneswar@gmail.com

Abstract - This paper presents the design and implementation of a single-cycle processor based on the RV32I instruction set architecture (ISA) using Verilog HDL. The processor supports basic 32-bit operations such as arithmetic, logical, memory access, and control flow instructions, covering common instruction formats including R-type, I-type, S-type, B-type, and J-type. The overall design is divided into modular blocks such as the Program Counter, Control Unit, Register File, Arithmetic Logic Unit (ALU), and memory units, making thearchitecture easier to understand and implement. The functionality of the processor is verified through behavioral simulation and RTL analysis using the Xilinx Vivado tool. The simulation results show correct instruction execution, including proper register updates, memory read/write operations, and branch handling. In addition to simulation, synthesis and implementation steps are also carried out to analyze how the design maps onto hardware resources