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Design and Implementation of AHB-To-APB Bridge with CRC-Based Error Detection

Divya K
B.E - IV Year Department of ECE Chettinad College
of Engineering and Technology Karur,Tamilnadu, India senthilkumar37378@gmail.com

Gowsalya B
B.E - IV Year Department of ECE Chettinad Collegeof Engineering and Technology karur,Tamilnadu, India
krkarthi601@gmail.com

Jeevitha D
B.E - IV Year Department of ECE Chettinad College
of Engineering and Technology karur,Tamilnadu, India duraikannujeevitha@gmail.com

Jeevitha M
B.E - IV Year Department of ECE Chettinad College
of Engineering and Technology karur,Tamilnadu, India
ragulsutha77@gmail.com

Ragavi D
Assistant Professor Department of ECE Chettinad College
of Engineering and Technology karur,Tamilnadu, India ragaviece@chettinadtech.ac.in

Abstract—Modern System-on-Chip (SoC) architectures incor- porate multiple high speed and low-power components, empha-sizing the need for efficient communication. The AMBA protocol helps standardize interactions between different components within an SoC.This paper explores the design and implementation of an AHB-to-APB bridge using SystemVerilog. The bridge enables efficient data transfer between the Advanced High- Performance Bus (AHB) and the Advanced Peripheral Bus (APB), ensuring seamless compatibility and smooth
operation. Additionally, a Cyclic Redundancy Check (CRC) mechanism is integrated to detect and prevent data corruption during transmission. By reducing latency and improving reliability, this approach enhances the overall efficiency of SoC architectures. The correctness and performance of the bridge were verified through simulation.
Index Terms—AMBA, AHB, APB, SystemVerilog, SoC, Error Detection, CRC.