Design of a 32-bit FPGA layout based on ALU employing reversible logic gates

Jyothi Thinnaluri1, Meduru Dilip2, Uppara Jaishnavi3, Gali Chandra Sekhar Reddy4,
PutakalaGovardhan5
1Assistant Professor, Department of ECE, Annamacharya Institute of Technology and Sciences, Tirupati,
Andhra Pradesh, jtiaits@gmail.com
2Student Department of ECE, Annamacharya Institute of Technology and Sciences, Tirupati,
Andhra Pradesh, dilipmeduru971@gmail.com
3Student Department of ECE, Annamacharya Institute of Technology and Sciences, Tirupati,
Andhra Pradesh, jaishnaviuppara@gmail.com
4Student Department of ECE, Annamacharya Institute of Technology and Sciences, Tirupati,
Andhra Pradesh, chandrasekharreddy8886@gmail.com
5Student Department of ECE, Annamacharya Institute of Technology and Sciences, Tirupati,
Andhra Pradesh, govardhanyadav3830@gmail.com

Abstract - The Arithmetic Logic Unit (ALU) is crucial core part of processors, responsible for performing arithmetic and logical operations. Traditional ALUs are designed by using irreversible logic gates that leads to higher power consumption and increased delay due to the loss of information during computation. To overcome from these limitations, in the proposed 32-bit ALU model is designed based on reversible logic gates. The main objective of this model is to improve both energy efficiency and performance by reduce the input information loss. The proposed design reduces power dissipation while supporting a wide range of arithmetic and logical operations. This occupies 3% of the totalmemory in FPGA and saves area by 91% compared to the traditional design. The implementation shows better performance in terms of speed, area and power, this is suitable solution for low-power VLSI applications. Keywords — Reversible Logic Gates, 32-bit ALU, LowPower Design, FPGA Implementation, Energy Efficient Computing.