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Design of High Speed UART Protocol with CRC Error Detection at IP Level

S. Mahammad Fayaz

M.Tech Student,

 Department of ECE,

JNTUA CEA, Anantapur,

Andhra Pradesh, India.

Mr. K. Srinivasa Rao M.Tech, (Ph.D)

Assistant Professor

 Department of ECE,

JNTUA CEA, Anantapur,

Andhra Pradesh, India

Abstract—In this project, we present the design and implementation of a Custom High-Speed UART Protocol with CRC Error Detection at the IP level, specifically tailored for applications that demand reliable and high-speed data transmission, such as medical imaging systems. Traditional UART protocols utilize parity bits for error detection, which are limited in their ability to detect multi-bit or burst errors, thus compromising data integrity in noise-prone environments. To overcome this limitation, the proposed design replaces parity-based error detection with CRC (Cyclic Redundancy Check) logic, enabling more robust and accurate error identification. The system is designed with a modular architecture, consisting of a UART Transmitter and Receiver integrated with CRC Generator and Checker modules. The transmission process is controlled by a finite state machine that includes framing with start, data, CRC, and stop bits. The protocol supports 8-bit data width,  and CRC-16 configurations, and operates at a high baud rate of 16 Mbps with a system clock of 256 MHz, ensuring compatibility with high-throughput applications. The design is described in Verilog HDL, simulated using Xilinx Vivado, and verified through waveform analysis. The simulation results confirm correct data transmission and reception with CRC validation, and demonstrate the system's ability to detect and flag data corruption. This work enhances the reliability of UART communication and establishes a foundation for integrating error-resilient UART interfaces into modern SoC platforms.

Keywords— High Speed UART, CRC Error Detection, CRC-16, Transmitter, Receiver, CRC Generator and Checker, Medical imaging, IP Core