Design of Low Power TG - Based Finfet D Flip-Flop for Memory Cell Architecture

Mr. E. Satheesh Kumar , M .Tech,
Assistant Professor,Department of Electronics andCommunication Engineering,
Annamacharya Institute ofTechnology and Sciences, Tirupati,esatheesh79@gmail.com
Surekha Allam ,B .Tech,Department of Electronics andCommunicaion Engineering,
Annamacharya Institute ofTechnology and Sciences,
Tirupati,allamsurekha@gmail.com
Muzahid Mandem ,B .Tech,
Department of Electronics and Communication Engineering,
Annamacharya Institute of Technology and Sciences,
Tirupati,muzzumuzahid008@gmail.com
Sravanthi Elavuru,B .Tech,
Department of Electronics andCommunication Engineering,
Annamacharya Institute ofTechnology and Sciences,
Tirupati,sravs7334@gmail.com
Sathish Kumar Koppu,B .Tech,
Department of Electronics and CommunicationEngineering,
Annamacharya Institute of Technology and Sciences, Tirupati,
koppusathishkumar12@gmail.com

ABSTRACT:This presents the design and analysis of a low-power transmission gate (TG)- based D flip-flop implemented using FinFET technology. The proposed architecture aims to enhance power efficiency and reduce leakage power compared to conventional CMOS-baseddesigns. Performance evaluation is carried out by analyzing key parameters, including static power, dynamic power, and average power consumption, while ensuring reliable operation at high frequencies. Simulation results demonstrate that the TG-based FinFET D flip-flop achieves improved performance with notable power savings, making it suitable for energy-efficient memory cell applications. The proposed design exhibits a reduction in average power consumption of up to 9.36% when compared to existing designs. These results validate the effectiveness of FinFET technology for low-power, high-performance memory circuits. KEYWORDS : FinFET technology, D flip-flop, TGFF,
Memory cell,CMOS