Enhanced Self-Test and Fault Localization in VLSI Circuit Using a 32-bit LFSR
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Enhanced Self-Test and Fault Localization in VLSI Circuit Using a 32-bit LFSR
Authors:
M. Pardha Saradhi , M.Tiny Serina, K. Sai Sravya, M. Pavithra, P. Ankitha
Abstract – An Enhanced Self-Test and Fault Localization System (STFLS) improves fault detection accuracy in digital circuits. A 32-bit LFSR-based Pseudo-Random Pattern Generator generated test patterns, establishing a fault-free reference for precise comparison. Faults were identified by detecting deviations from the stored baseline outputs to ensure accurate localization. The system was implemented in Verilog HDL and simulated using Xilinx Vivado, thereby enhancing traditional self-test techniques. This approach is highly effective for VLSI testing, hardware verification, and fault analysis, and ensures improved system reliability and performance in complex digital architectures.
Key Words: Fault Localization, LFSR, VLSI Testing Hardware Verification, FPGA Implementation