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Fault Tolerant Low Power Multiplier for Smart Edge Devices

Dondapati Leela Bhuvaneswari¹, Muppidi Chaitanya Sai², Panchakarla Viswaja³,
Pallikanti Swami Raj⁴
¹Assistant Professor, Department of Electronics and Communication Engineering, Seshadri Rao
Gudlavalleru Engineering College, Gudlavalleru, India
² ³ ⁴ Department of Electronics and Communication Engineering, Seshadri Rao Gudlavalleru
Engineering College, Gudlavalleru, India

ABSTRACT:Edge computing platforms require energy-efficient arithmetic units to handle real-time, data-intensive workloads under strict power and area constraints. Conventional multipliers consume considerable power and hardware resources, making them less suitable for resourcelimited edge devices. This work proposes a low-power approximate multiplier architecture that employs an optimized 5:2 approximate compressor to improve partial product reduction efficiency. By reducing the number of reduction stages and switching activity, the design achieves lower dynamic power consumption and improved power delay product (PDP) while maintaining acceptable accuracy for error-tolerant applications. System-level validation using MATLAB-based image processing demonstrates that the propoed multiplier is well suited for signal processing, image processing, and deep neural network workloads inresource-constrained edge environments.