Implementation of an Advanced 32-Bit MIPS Softcore Processor on FPGA

R.Senthamil Selvan

Department of Electronics and Communication Engineering Annamacharya Institute of Technology and Sciences

Tirupati, India selvasenthamil2614@gmail.com

Thangam Yugandhar Reddy

Department of Electronics and Communication Engineering Annamacharya Institute of Technology and Sciences

Tirupati, India yugareddyyuga@gmail.com

Gorintla Vishnu

Department of Electronics and Communication Engineering Annamacharya Institute of Technology and Sciences

Tirupati, India Vishnunanistuv@gmail.com

Kuruva Vijay Kumar

Department of Electronics and Communication EngineeringAnnamacharya Institute of Technology and Sciences

Tirupati,India kuruvavijay78@gmail.com

Sanjamala Shyam Sundar

Department of Electronics and Communication Engineering Annamacharya Institute of Technology and Sciences

Tirupati, India sanjamalashyamsmile143@gmail.com

Abstract:This project presents the design and FPGA implementation of an advanced 32-bit MIPS softcore processor, developed using Verilog HDL and targeted for the Xilinx Artix-7 FPGA on the Nexys DDR4 development board. The processor extends the classic MIPS architecture with a five-stage pipeline (fetch, decode, execute, memory, write-back) and includes support for arithmetic, logical, memory access, and conditional branch instructions. Key enhancements such as hazard detection, data forwarding, and a lightweight memory-mapped peripheral interface (UART, GPIO, timer) are integrated to improve performance and usability .The design is synthesized and implemented using the Xilinx Vivado toolchain, with optimization techniques applied to achieve efficient resource utilization and a clock frequency of 100 MHz. Verification is carried out through simulation, unit testbenches, and hardware testing using representative assembly programs. The resulting softcore processor occupies approximately 30% of slice LUTs and 20% of flip-flops, leaving ample space for additional user logic. This work demonstrates a flexible, open-source MIPS softcore suitable for embedded system prototyping, education, and further research in computer architecture on reconfigurable hardware.Keywords: Verilog Processor, 32-bit architecture, Symmetric Instruction Set, Overloaded Instruction Set Architecture, Softcore Processor, FPGA Implementation, SOMA Execution, Hardware Design, Digital Circuit Design, Computer Architecture, Processor Performance Optimization