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Implementation of SEC-DED-DAEC Codes using Mentor Graphics

Dr. G. SATEESH KUMAR, M. SAHITHI, B. SRUTHI, B. CHAKRADHAR, B. HITHUSEKHAR, S. KODANDA RAMA KALYAN

*PROFFESOR, DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING, ADITYA INSTITUTE OF TECHNOLOGY AND MANAGEMENT, TEKKALI.

**STUDENT, DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING,

ADITYA INSTITUTE OF TECHNOLOGY AND MANAGEMENT, TEKKALI.

ABSTRACT

Correction of a single error Double Error Detection (SEC-DED) and Double Adjacent Error Correction (DAEC) are prominent error correction algorithms used in computer memory systems to detect and fix errors that arise during data transfer. In this research, we want to put these ideas into practice and assess how well they work through simulations and experiments. We will research the trade-offs between these strategies' efficiency and reliability and contrast them with other error correction techniques. Our research will involve designing and putting error detection and correction procedures into circuits and algorithms for DAEC and SEC-DED. We will also investigate other methods, including parallel processing and error checking mechanisms, to enhance the performance of these strategies. Our findings may also have applications in other domains where error correction is important, such as communication systems and medical equipment. They will help us understand and enhance error correction techniques used in computer memory systems.