Performance of 16-Bit Re-Configurable Multiplier Architecture

Dilip Kumar Nuthalapati
Assistant Professor,Department of ECE,
Annamacharya Institute of Technology and Sciences, Tirupati, India
dilipkumar.aits@gmail.com
Deekshitha Reddy B
B.Tech, Departament of ECE,Annamacharya Institute of
Technology and Sciences, Tirupati,Indiareddydeekshitha218@gmail.com
Geethika Bandaru
B.Tech, Department of ECE, Annamacharya Institute of Technology and Sciences, Tirupati, India
bandarugeethika16@gmail.com
Harsha Vardhan B
B.Tech, Department of ECE,Annamacharya Institute of Technology and sciences, Tirupati, India
harshabommu4@gmail.com
Deepthi Chittibona
B.Tech, Department of ECE,Annamacharya Institute of
Technology and Sciences, Tirupati,Indiadeepulucky479@gmail.com

Abstract—This paper presents a 16-bit Reconfigurable Approximate Multiplier (ReM) architecture designed for energy efficient neuromorphic computing applications. The proposed design integrates dynamic precision scaling and lightweight redundancy to achieve improved power–area efficiency while maintaining acceptable computational accuracy. Multiple precision modes enable adaptive operation based on workload requirements, allowing the multiplier to balance energy consumption and performance dynamically. A Precision Control Unit (PCU) regulates approximation levels, while a Reduced-Precision Redundancy mechanism enhances reliability with minimal hardware overhead. The architecture is implemented and validated on FPGA using Xilinx Vivado to evaluate delay, power consumption, and resource utilization. Experimental results demonstrate that the proposed design significantly reduces overall on-chip power consumption while maintaining stable performance, with only a moderate increase in logic resource utilization. Behavioral simulation confirms correct functional operation under different precision modes. The modular and scalable structure of the proposed design makes it suitable for Spiking Neural Networks (SNNs) and other energy-constrained edge AI applications, offering an effective trade-off between efficiency, flexibility, and reliability. KeyWords—Neuromorphic Architecture, Spiking Neural Networks(SNNs), Approximate Arithmetic Units, Recofigurable Hardware