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Prevention of Rowhammer Attacks in MIV-Based 3D-DRAM using Target Row Refresh

 

 

M. Dhanunjaya

MTech VLSISD,

Department of Electronics and Communication Engineering ,

JNTUACEA, Anantapur

Andhra Pradesh, India.

dhanunjaya16th@gmail.com JNTUACEA, Anantapur,

 

 

2Dr. S. Chandra Mohan Reddy

Professor

Department of Electronics and Communication Engineering

JNTUACEA, Anantapur

Andhra Pradesh, India

cmr.ece@jntua.ac.in

 

 

Abstract— As Dynamic Random-Access Memory (DRAM) devices scale down and shift to 3D architectures using Monolithic Inter-layer Vias (MIVs) and Through-Silicon Vias (TSVs), they become increasingly vulnerable to disturbance-based attacks such as Rowhammer. This phenomenon occurs when repeated activation of specific memory rows causes voltage interference in neighbouring rows, potentially flipping stored bits and compromising data integrity. This project investigates the Rowhammer effect through NGSPICE simulations of 3D DRAM cells, accurately modelling aggressor, and victim rows with parasitic coupling. To mitigate such attacks, we implement a Target Row Refresh (TRR) strategy that identifies frequently accessed rows and pre-emptively refreshes adjacent victim rows. Our results confirm that TRR effectively prevents charge leakage and bit flips, even under aggressive hammering. The presence of MIVs enhances bandwidth and compactness in 3D DRAM but also increases inter-row coupling, making TRR protection even more critical. This work highlights a practical defines mechanism and deepens the understanding of physical vulnerabilities in modern memory systems.

Keywords— Rowhammer, 3D DRAM, MIV, Target Row Refresh, NGSPICE Simulation, Bit Flip Prevention, Memory Security, Victim Row Stability.

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