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RHBD SRAM Cell using Transmission Gate for Aerospace Application

1K. Naveen,

M.Tech (VLSI SD),

Department of Electronics &Communication Engineering

JNTUA College of Engineering Ananthapur ,

naveenveeru3@gmail.com

2S. Chandra Mohan Reddy

Professor,

Department of Electrnics &Communication Engineering

JNTUA College of Engineering Ananthapur

cmr.ece@jntua.ac.in

Abstract— As CMOS technology advances toward smaller feature sizes, Static Random-Access Memory (SRAM) cells implemented in aerospace environments face growing susceptibility to radiation-induced disturbances like Single Event Upsets (SEUs) and Single Event Multi-Node Upsets (SEMNUs). This paper presents an enhanced 12-transistor (12T) SRAM cell based on Transmission Gates (TG), specifically engineered to improve radiation tolerance, energy efficiency, and operational reliability in harsh space environments. The proposed TG-based SRAM incorporates a robust feedback mechanism that enables rapid recovery from SEUs and SEMNUs across all sensitive nodes. Comparative analysis with existing designs EDP12T, RHM12T, RHD12T, QUATRO12T, QUCCE12T, and S8P4N16T demonstrates significant performance gains. Specifically, the proposed cell enhances Read Static Noise Margin (RSNM) by up to 2.32× and improves write margin while minimizing energy consumption during memory operations. Monte Carlo and HSPICE simulation results confirm superior performance under process and radiation variations. Notably, the proposed design achieves a 36.9% improvement in write stability (WWTV) compared to EDP12T, while also reducing read/write power dissipation. Unlike some existing designs that suffer from read delay penalties, the TG-based cell sustains fast access speeds with lower leakage and hold power. These advancements make the proposed SRAM architecture a promising solution for radiation-hardened memory in space and satellite platforms, where low power, high speed, and resilience to radiation are critical design requirements.

Keywords— Radiation-tolerant SRAM, Transmission Gate, Single Event Upset, SEU recovery, Low-power memory, 12T SRAM cell.