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Three Stage Comparator with High Speed and Low Kickback Using CMOS

*[1] K.Lavanya , S.Mounika[2] , P.Ajay Kumar[3]  ,V.Kavya[4]  , T.Prem Sai[5]  , SK.Farheena[6]

 *[1] Asst.professor,[2-6] UG Scholar, [1-6] Sir C R Reddy College Of Engineering1, Eluru, Andhrapradesh

*[1] lavanyasudeep@gmail.com

Abstract— In this research, we propose the design of a high-speed, low-kickback, three-stage comparator built on CMOS technology. This 1.2V supply-operated comparator circuit develops for use in high-speed ADCs. There are three parts to the proposed comparator circuit: a preamplifier, a latch, and a regeneration stage. The input signal amplifies in the preamplifier stage, producing a differential output signal. Once the movement from the preamplifier stage strengthens, it is stored in the latch stage until the regeneration stage is ready to utilize—simulations in CMOS technology to test the suggested comparator circuit. The voltage gain and switching speed of the three-stage comparator in this research improve over the standard two-stage comparators. The LT spice simulation results demonstrate the proposed comparator circuit's fast speed, minimal backlash, and low power consumption.

Index Terms— Preamplifier, High speed, Low kickback noise, Analog to digital converter.